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integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 block diagram pin configuration recommended application: ati chipset, p4 system, banias system output features: 2 - pairs of differential cpuclks (differential current mode) 1 - sdram @ 3.3v 8 - pci @3.3v (selectable 33/66 mhz) (2 free-running) 2 - agp @ 3.3v 2- 48mhz, @3.3v fixed. 1- 24/48mhz, @3.3v selectable by i 2 c (default is 24mhz) 3- ref @3.3v, 14.318mhz. features/benefits: support for intel banias power management features programmable output frequency, divider ratios, output rise/ falltime, output skew. programmable spread percentage for emi control. watchdog timer technology to reset system if system malfunctions. programmable watch dog safe frequency. support i 2 c index read/write and block read/write operations. supports spread spectrum for emi reduction; default is spread spectrum on. programmable timing control hub? for p 4 ? processor * these inputs have a 120k pull up to vdd. ** these inputs have a 120k pull down to gnd. advance information documents contain information on products in the formative or design phase development. characteristic data and other specific ations are design goals. ics reserves the right to change or discontinue these products without notice. third party brands and names are the property of their respective owners. 48-pin tssop & ssop power groups vddcpu = cpu vddpci = pciclk_f, pciclk vddsd = sdram avdd48 = 48mhz, 24mhz, fixed pll avdd = analog core pll vddagp= agp vddref = xtal, ref skew requirements vddref 1 48 vddsdr fs0/ref0 2 47 sdram_out fs1/ref1 3 46 gndsdr fs2/ref2 4 45 cpu_stop#* gndref 5 44 cpuclkt1 x1 6 43 cpuclkc1 x2 7 42 vddcpu gnd 8 41 gndcpu vdd 9 40 cpuclkt0 *vttpwr_gd/pd# 10 39 cpuclkc0 pci66/33#_sel 11 38 iref pci_stop#* 12 37 gnd vddpci 13 36 avdd fs3/pciclk_f0 14 35 sclk fs4/pciclk_f1 15 34 sdata pciclk016 33gndagp pciclk117 32agpclk0 gndpci 18 31 agpclk1 vddpci 19 30 vddagp pciclk220 29avdd48 pciclk321 2848mhz_0 pciclk422 2748mhz_1 pciclk5 23 26 24_48mhz/sel24_48#mhz** gndpci 24 25 gnd48 ics951402 pci-pci <350ps agp-agp <350ps cpu-agp <500ps cpu-pci <500ps cpu-sdram <1ns agp-pci agp leadin g <1ns i ref cpu divder pll2 pll1 spread spectr um 48mhz (0:1) 24_48mhz pciclk (5:0) agp (1:0) pciclk_f (1:0) 2 2 1 6 3 x1 x2 xtal osc sdram sdram_out pci divder stop s data sclk fs (4:0) pd# pci_stop# cpu_stop# pd#/vtt_pwrgd pci66/33#sel 24_48sel# control logic config. reg. / 2 ref (2:0) agp divder stop 2 2 cpuclkt (1:0) cpuclkc (1:0)
2 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 pin description pin number pin name type description 1 vddref pwr ref, xtal power supply, nominal 3.3v 2 fs0/ref0 i/o frequency select latch input pin / 14.318 mhz reference clock. 3 fs1/ref1 i/o frequency select latch input pin / 14.318 mhz reference clock. 4 fs2/ref2 i/o frequency select latch input pin / 14.318 mhz reference clock. 5 gndref pwr ground pin for the ref outputs. 6 x1 in crystal input, nominally 14.318mhz. 7 x2 out crystal output, nominally 14.318mhz 8 gnd pwr ground pin. 9 vdd pwr power supply, nominal 3.3v 10 *vttpwr_gd/pd# in this 3.3v lvttl input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. this is an active high input. / asynchronous active low input pin used to power down the device into a low power state. 11 pci66/33#_sel in selects all pci clock frequencies to be 33mhz or 66mhz. 0 = 33mhz , 1 = 66mhz 12 pci_stop#* in stops all pciclks besides the pciclk_f clocks at logic 0 level, when input low 13 vddpci pwr power supply for pci clocks, nominal 3.3v 14 fs3/pciclk_f0 i/o frequency select latch input pin / 3.3v pci free running clock output. 15 fs4/pciclk_f1 i/o frequency select latch input pin / 3.3v pci free running clock output. 16 pciclk0 out pci clock output. 17 pciclk1 out pci clock output. 18 gndpci pwr ground pin for the pci outputs 19 vddpci pwr power supply for pci clocks, nominal 3.3v 20 pciclk2 out pci clock output. 21 pciclk3 out pci clock output. 22 pciclk4 out pci clock output. 23 pciclk5 out pci clock output. 24 gndpci pwr ground pin for the pci outputs 25 gnd48 pwr ground pin for the 48mhz outputs 26 24_48mhz/sel24_48#mhz** i/o 24/48mhz clock output / latched select input for 24/48mhz output. 0=48mhz, 1 = 24mhz. 27 48mhz_1 out 48mhz clock output. 28 48mhz_0 out 48mhz clock output. 29 avdd48 pwr analog power for 48mhz outputs and fixed pll core, nominal 3.3v 30 vddagp pwr power supply for agp clocks, nominal 3.3v 31 agpclk1 out agp clock output 32 agpclk0 out agp clock output 33 gndagp pwr ground pin for the agp outputs 34 sdata i/o data pin for smbus circuitry, 5v tolerant. 35 sclk in clock pin of smbus circuitry, 5v tolerant. 36 avdd pwr 3.3v analog power pin for core pll 37 gnd pwr ground pin. 38 iref out this pin establishes the reference current for the differential current- mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 39 cpuclkc0 out complementary clock of differential pair cpu outputs. this clock is 180 degrees out of phase with the sdram clock. 40 cpuclkt0 out true clock of differential pair cpu outputs. this clock is in phase with the sdram clock 41 gndcpu pwr ground pin for the cpu outputs 42 vddcpu pwr supply for cpu clocks, 3.3v nominal 43 cpuclkc1 out complementary clock of differential pair cpu outputs. this clock is 180 degrees out of phase with the sdram clock. 44 cpuclkt1 out true clock of differential pair cpu outputs. this clock is in phase with the sdram clock 45 cpu_stop#* in stops all cpuclk besides the free running clocks 46 gndsdr pwr ground pin for the sdram outputs. 47 sdram_out out sdram seed clock output for external buffer 48 vddsdr pwr supply for sdram clocks, nominal 3.3v.
3 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 table 1: clock power management truth table byte 6 bit 6 byte 6 bit 7 pd# cpu_ stop stoppable cpu (not free-run) non-stop cpu (free-run) note 0 0 0 0 iref x 2 iref x 2 0 0 0 1 iref x 2 iref x 2 0 0 1 0 iref x 6 run 0 0 1 1 run run non tri-state mode 0 1 0 0 hi z iref x 2 0 1 0 1 hi z iref x 2 0 1 1 0 hi z run 0 1 1 1 run run cpu_stop# tri-state mode 1 0 0 0 hi z hi z 1 0 0 1 hi z hi z 1 0 1 0 irefx6 run 1 0 1 1 run run pd# & tri-state mode 1 1 0 0 hi z hi z 1 1 0 1 hi z hi z 1 1 1 0 hi z run 1 1 1 1 run run pd# & cpu_stop# tri-state mode
4 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 *see notes on the following page . general i 2 c serial interface information for the ics951402 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
5 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 serial configuration command bitmap fs4 fs3 fs2 fs1 fs0 00000 100.00 100.00 66.67 33.33 14.318 48.008 0 0 0 0 1 133.34 133.34 66.67 33.33 14.318 48.008 0 0 0 1 0 200.01 200.01 66.67 33.33 14.318 48.008 0 0 0 1 1 166.65 166.65 66.66 33.33 14.318 48.008 0 0 1 0 0 100.00 133.34 66.67 33.33 14.318 48.008 0 0 1 0 1 133.34 100.00 66.67 33.33 14.318 48.008 0 0 1 1 0 133.16 166.45 66.58 33.29 14.318 48.008 0 0 1 1 1 166.45 133.16 66.58 33.29 14.318 48.008 0 1 0 0 0 105.00 105.00 70.00 35.00 14.318 48.008 0 1 0 0 1 140.00 140.00 70.00 35.00 14.318 48.008 0 1 0 1 0 66.67 66.67 66.67 33.33 14.318 48.008 0 1 0 1 1 175.00 175.00 70.00 35.00 14.318 48.008 0 1 1 0 0 109.99 109.99 73.33 36.66 14.318 48.008 0 1 1 0 1 146.65 146.65 73.33 36.66 14.318 48.008 0 1 1 1 0 210.00 210.00 70.00 35.00 14.318 48.008 01111 183.27 183.27 73.31 36.65 14.318 48.008 1 0 0 0 0 99.51 99.51 66.34 33.17 14.318 48.008 1 0 0 0 1 132.68 132.68 66.34 33.17 14.318 48.008 1 0 0 1 0 199.02 199.02 66.34 33.17 14.318 48.008 1 0 0 1 1 165.85 165.85 66.34 33.17 14.318 48.008 1 0 1 0 0 99.51 132.68 66.34 33.17 14.318 48.008 1 0 1 0 1 132.68 99.51 66.34 33.17 14.318 48.008 1 0 1 1 0 132.59 165.73 66.29 33.15 14.318 48.008 10111 165.73 132.59 66.29 33.15 14.318 48.008 1 1 0 0 0 99.39 99.39 66.26 33.13 14.318 48.008 1 1 0 0 1 132.51 132.51 66.26 33.13 14.318 48.008 1 1 0 1 0 198.77 198.77 66.26 33.13 14.318 48.008 1 1 0 1 1 165.64 165.64 66.25 33.13 14.318 48.008 1 1 1 0 0 99.39 132.51 66.26 33.13 14.318 48.008 1 1 1 0 1 132.51 99.39 66.26 33.13 14.318 48.008 1 1 1 1 0 132.36 165.45 66.18 33.09 14.318 48.008 11111 165.45 132.36 66.18 33.09 14.318 48.008 3v66 mhz pci mhz sdram mhz down spread -0.8% spread off or center spread +/-0.3% down spread -0.6% cpu mhz ref mhz usb/dot mhz with spread enabled?
6 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 i 2 c table : reserved register byte 0 pin # name control function type 0 1 pwd bit 7 - reserved reserved rw - - 1 bit 6 - reserved reserved rw - - 1 bit 5 - reserved reserved rw - - 1 bit 4 - reserved reserved rw - - 1 bit 3 - reserved reserved rw - - 1 bit 2 - reserved reserved rw - - 1 bit 1 - reserved reserved rw - - 1 bit 0 - reserved reserved rw - - 1 i 2 c table : reserved register byte 1 pin # name control function type 0 1 pwd bit 7 - reserved reserved rw - - 1 bit 6 - reserved reserved rw - - 1 bit 5 - reserved reserved rw - - 1 bit 4 - reserved reserved rw - - 1 bit 3 - reserved reserved rw - - 1 bit 2 - reserved reserved rw - - 1 bit 1 - reserved reserved rw - - 1 bit 0 - reserved reserved rw - - 1 i 2 c table : reserved register byte 2 pin # name control function type 0 1 pwd bit 7 - reserved reserved rw - - 1 bit 6 - reserved reserved rw - - 1 bit 5 - reserved reserved rw - - 1 bit 4 - reserved reserved rw - - 1 bit 3 - reserved reserved rw - - 1 bit 2 - reserved reserved rw - - 1 bit 1 - reserved reserved rw - - 1 bit 0 - reserved reserved rw - - 1
7 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 i 2 c table : reserved register byte 3 pin # name control function type 0 1 pwd bit 7 - reserved reserved rw - - 1 bit 6 - reserved reserved rw - - 1 bit 5 - reserved reserved rw - - 1 bit 4 - reserved reserved rw - - 1 bit 3 - reserved reserved rw - - 1 bit 2 - reserved reserved rw - - 1 bit 1 - reserved reserved rw - - 1 bit 0 - reserved reserved rw - - 1 i 2 c table : functionality and frequency select register byte 4 pin # name control function type 0 1 pwd bit 7 - fs3 freq select bit 7 rw 0 bit 6 - fs2 freq select bit 6 rw 0 bit 5 - fs1 freq select bit 5 rw 0 bit 4 - fs0 freq select bit 4 rw see frequency table 0 bit 3 - fs source frequency h/w or iic select rw latch input iic 0 bit 2 - fs4 freq select bit 2 rw see frequency table 0 bit 1 - ss_en spread enable rw off on 1 bit 0 - all outputs output control rw normal tri-state 0 note: if byte4 bit1 = 0 then fs4=0 i 2 c table : output control and read back register byte 5 pin # name control function type 0 1 pwd bit 7 31 agp1 output control rw disable enable 1 bit 6 32 agp0 output control rw disable enable 1 bit 5 26 24_48#sel 24 or 48 select rw 48mhz 24mhz x bit 4 - fs4rb fs4 read back r - - x bit 3 - fs3rb fs3 read back r - - x bit 2 - fs2rb fs2 read back r - - x bit 1 - fs1rb fs1 read back r - - x bit 0 - fs0rb fs0 read back r - - x
8 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 i 2 c table : output control register byte 6 pin # name control function type 0 1 pwd bit 7 - cpu_stop# cpu stop status rw 1 bit 6 - pd# pd# status rw see table 1: truth table on page 3 1 bit 5 - pci_f0 free-run control rw free not free 0 bit 4 - pci_f1 free-run control rw free not free 0 bit 3 - cput/c_0 free-run control rw free not free 1 bit 2 - cput/c_1 free-run control rw free not free 1 bit 1 40,39 cput/c_0 output control rw disable enable 1 bit 0 44,43 cput/c_1 output control rw disable enable 1 i 2 c table : output control register byte 7 pin # name control function type 0 1 pwd bit 7 15 pciclk_f1 output control rw disable enable 1 bit 6 14 pciclk_f0 output control rw disable enable 1 bit 5 23 pciclk5 output control rw disable enable 1 bit 4 22 pciclk4 output control rw disable enable 1 bit 3 21 pciclk3 output control rw disable enable 1 bit 2 20 pciclk2 output control rw disable enable 1 bit 1 17 pciclk1 output control rw disable enable 1 bit 0 16 pciclk0 output control rw disable enable 1 i 2 c table : byte count register byte 8 pin # name control function type 0 1 pwd bit 7 - bc7 rw - - 0 bit 6 - bc6 rw - - 0 bit 5 - bc5 rw - - 0 bit 4 - bc4 rw - - 0 bit 3 - bc3 rw - - 1 bit 2 - bc2 rw - - 1 bit 1 - bc1 rw - - 1 bit 0 - bc0 writing to this register will configure how many bytes will be read back, default is 0f = 15 bytes. rw - - 1
9 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 i 2 c table: watchdog timer register byte 9 pin # name control function type 0 1 pwd bit 7 - wd7 rw - - 0 bit 6 - wd6 rw - - 0 bit 5 - wd5 rw - - 0 bit 4 - wd4 rw - - 1 bit 3 - wd3 rw - - 0 bit 2 - wd2 rw - - 0 bit 1 - wd1 rw - - 0 bit 0 - wd0 these bits represent x*293ms the watchdog timer will wait before it goes to alarm mode. default is 16 x 293ms = 4 .688 seconds rw - - 0 i 2 c table : wd timer control register byte 10 pin # name control function type 0 1 pwd bit 7 - m/nen m/ n programming enable rw latched inputs iic prog. b (11:17) 0 bit 6 - wden watchdog enable rw disable enable 0 bit 5 - wdstatus wd status control rw off on 0 bit 4 - wd sf4 rw - - 1 bit 3 - wd sf3 rw - - 0 bit 2 - wd sf2 rw - - 0 bit 1 - wd sf1 rw - - 0 bit 0 - wd sf0 writing to these bit will configure the safe frequency as byte 0 bit (6:0 ) rw - - 0 note: if byte4 bit1 = 0 then fs4=0 i 2 c table: vco frequency control register byte 11 pin # name control function type 0 1 pwd bit 7 - n div8 n divider bit 8 rw - - x bit 6 - m div6 rw - - x bit 5 - m div5 rw - - x bit 4 - m div4 rw - - x bit 3 - m div3 rw - - x bit 2 - m div2 rw - - x bit 1 - m div1 rw - - x bit 0 - m div0 the decimal representation of m div (6:0) is equal to reference divider value. default at power up = latch-in or byte 0 rom table. rw - - x
10 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 i 2 c table: vco frequency control register byte 12 pin # name control function type 0 1 pwd bit 7 - n div7 rw - - x bit 6 - n div6 rw - - x bit 5 - n div5 rw - - x bit 4 - n div4 rw - - x bit 3 - n div3 rw - - x bit 2 - n div2 rw - - x bit 1 - n div1 rw - - x bit 0 - n div0 the decimal representation of n div (8:0) is equal to vco divider value. default at power up = latch-in or byte 0 rom table. rw - - x i 2 c table: spread spectrum control register byte 13 pin # name control function type 0 1 pwd bit 7 - ssp7 rw - - x bit 6 - ssp6 rw - - x bit 5 - ssp5 rw - - x bit 4 - ssp4 rw - - x bit 3 - ssp3 rw - - x bit 2 - ssp2 rw - - x bit 1 - ssp1 rw - - x bit 0 - ssp0 these spread spectrum bits will program the spread percentage. it is recommended to use ics spread % table for spread programming. rw - - x i 2 c table: spread spectrum control register byte 14 pin # name control function type 0 1 pwd bit 7 - reserved reserved r - - x bit 6 - reserved reserved r - - x bit 5 - reserved reserved r - - x bit 4 - ssp12 rw - - x bit 3 - ssp11 rw - - x bit 2 - ssp10 rw - - x bit 1 - ssp9 rw - - x bit 0 - ssp8 it is recommended to use ics spread % table for spread programming. rw - - x
11 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 i 2 c table : output divider control register byte 15 pin # name control function type 0 1 pwd bit 7 - sd div3 rw x bit 6 - sd div2 rw x bit 5 - sd div1 rw x bit 4 - sd div0 sdram divider ratio can be configured via these 4 bits individually. rw see table 2: divider ratio combination table x bit 3 - cpu div3 rw x bit 2 - cpu div2 rw x bit 1 - cpu div1 rw x bit 0 - cpu div0 cpu divider ratio can be configured via these 4 bits individually. rw see table 2: divider ratio combination table x table 2: cpu, sdram, agp and pci66 divider ratio combination table divider (3:2) bit 00 01 10 11 msb 1 2 4 8 00 0000 2 0100 4 1000 8 1100 16 01 0001 3 0101 6 1001 12 1101 24 10 0010 5 0110 10 1010 20 1110 40 11 0011 7 0111 14 1011 28 1111 56 divider (1:0) lsb address div address div address div address div table 3: pci33 divider ratio combination table divider (3:2) bit 00 01 10 11 msb 1 2 4 8 00 0000 4 0100 8 1000 16 1100 32 01 0001 3 0101 6 1001 12 1101 24 10 0010 5 0110 10 1010 20 1110 40 11 0011 7 0111 14 1011 28 1111 56 divider (1:0) lsb address div address div address div address div
12 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 i 2 c table : output divider control register byte 16 pin # name control function type 0 1 pwd bit 7 - agp div3 rw x bit 6 - agp div2 rw x bit 5 - agp div1 rw x bit 4 - agp div0 agp divider ratio can be configured via these 4 bits individually rw see table 2: divider ratio combination table x bit 3 - reserved reserved rw - - x bit 2 - reserved reserved rw - - x bit 1 - reserved reserved rw - - x bit 0 - reserved reserved rw - - x i 2 c table : output divider control register byte 17 pin # name control function type 0 1 pwd bit 7 - agpinv agp phase invert rw default inverse x bit 6 - reserved reserved rw - - x bit 5 - sdinv sdram phase invert rw default inverse x bit 4 - cpuinv cpu phase invert rw default inverse x bit 3 - pcidiv3 rw x bit 2 - pcidiv3 rw x bit 1 - pcidiv3 rw x bit 0 - pcidiv3 pci divider ratio can be configured via these 4 bits individually rw see table 2 & 3: divider ratio combination table x i 2 c table : group skew control register byte 18 pin # name control function type 0 1 pwd bit 7 - cpuskw3 rw 1 bit 6 - cpuskw2 cput skew control rw see 2-bit skew control at table 4 0 bit 5 - sdskw3 rw 0 bit 4 - sdskw2 sdram skew control rw see 2-bit skew control at table 4 1 bit 3 - reserved reserved rw - - 1 bit 2 - reserved reserved rw - - 1 bit 1 - reserved reserved rw - - 1 bit 0 - reserved reserved rw - - 1
13 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 table 4: skew specification on output mode bit3 bit2 bit1 bit0 skew in ps 0 0 x x 500 0 1 x x 750 1 0 x x 1000 1 1 x x 1250 i 2 c table : group skew control register byte 19 pin # name control function type 0 1 pwd bit 7 - reserved reserved rw - - 0 bit 6 - reserved reserved rw - - 0 bit 5 - reserved reserved rw - - 0 bit 4 - reserved reserved rw - - 0 bit 3 - agpskw3 rw 0 bit 2 - agpskw2 agp skew control rw see 2-bit skew control at table 4 0 bit 1 - reserved reserved rw - - 0 bit 0 - reserved reserved rw - - 0 i 2 c table : group skew control register byte 20 pin # name control function type 0 1 pwd bit 7 - pciskw3 rw 0 bit 6 - pciskw2 pci_f [1:0] skew control rw see 2-bit skew control at table 4 0 bit 5 - reserved reserved rw - - 0 bit 4 - reserved reserved rw - - 0 bit 3 - pciskw1 rw 0 bit 2 - pciskw0 pci [5:0] skew control rw see 2-bit skew control at table 4 0 bit 1 - reserved reserved rw - - 0 bit 0 - reserved reserved rw - - 0
14 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 i 2 c table : slew rate control register byte 21 pin # name control function type 0 1 pwd bit 7 - 24_48slw1 rw - - 0 bit 6 - 24_48slw0 24_48 slew rate control rw - - 0 bit 5 - agpslw1 rw - - 0 bit 4 - agpslw0 agp slew rate control rw - - 0 bit 3 - reserved reserved rw - - 0 bit 2 - reserved reserved rw - - 0 bit 1 - refslw1 rw - - 0 bit 0 - refslw0 ref slew rate control rw - - 0 i 2 c table : slew rate control register byte 22 pin # name control function type 0 1 pwd bit 7 - sdslw1 rw - - 0 bit 6 - sdslw0 sdram slew rate control rw - - 0 bit 5 - reserved reserved rw - - 0 bit 4 - reserved reserved rw - - 0 bit 3 - pcislw1 rw - - 0 bit 2 - pcislw0 pci_f slew rate control rw - - 0 bit 1 - pcislw1 rw - - 0 bit 0 - pcislw0 pci slew rate control rw - - 0 i 2 c table : output control register byte 23 pin # name control function type 0 1 pwd bit 7 - reserved reserved - - - x bit 6 27 48mhz_1 output control rw disable enable 1 bit 5 47 sdram output control rw disable enable 1 bit 4 28 48mhz_0 output control rw disable enable 1 bit 3 26 24_48mhz output control rw disable enable 1 bit 2 4 ref2 output control rw disable enable 1 bit 1 3 ref1 output control rw disable enable 1 bit 0 2 ref0 output control rw disable enable 1
15 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 i 2 c table : reserved control register byte 24 pin # name control function type 0 1 pwd bit 7 - reserved reserved rw - - 0 bit 6 - reserved reserved rw - - 0 bit 5 - reserved reserved rw - - 0 bit 4 - reserved reserved rw - - 0 bit 3 - reserved reserved rw - - 0 bit 2 - reserved reserved rw - - 0 bit 1 - reserved reserved rw - - 0 bit 0 - reserved reserved rw - - 0 i 2 c table : reserved control register byte 25 pin # name control function type 0 1 pwd bit 7 - reserved reserved rw - - 0 bit 6 - reserved reserved rw - - 0 bit 5 - reserved reserved rw - - 0 bit 4 - reserved reserved rw - - 0 bit 3 - reserved reserved rw - - 0 bit 2 - reserved reserved rw - - 0 bit 1 - reserved reserved rw - - 0 bit 0 - reserved reserved rw - - 0
16 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. core supply voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 v i/o supply voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . ?65c to +150c case temperature . . . . . . . . . . . . . . . . . . . . . . . . 115c electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units input high voltage v ih 2 v dd +0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in = v d d -5 5 ma i il1 v in = 0 v; inputs with no pull-up resistors -5 ma i il2 v in = 0 v; inputs with pull-up resistors -200 operating supply current i dd3.3op c l = full load; select @ 100 mhz 229 230 360 ma i dd3.3op c l =full load; select @ 133 mhz 220 233 360 ma powerdown current i dd3.3p d iref=5 ma 38.1 45 ma input frequency f i v dd = 3.3 v 14.32 mhz pin inductance l p in 7nh c in logic inputs 5 pf c ou t output pin capacitance 6 pf c inx x1 & x2 pins 27 36 45 pf clk stabilization 1,2 t stab from powerup or deassertion of powerdown to 1st clock. 11.8 ms t pzh ,t pzl output enable delay (all outputs) 1 10 ns t phz ,t plz output disable delay (all outputs) 1 10 ns 1 guaranteed by design, not 100% tested in production. 2 see timin g dia g rams for buffered and un-buffered timin g requirements. delay 1 input capacitance 1 input low current
17 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 electrical characteristics - cpu (0.7v select) t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units current source output impedance zo 1 v o = v x 3000 ? output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.4 volta g e hi g hvhi g h 660 710 850 volta g e lo w vlow -150 0 150 max volta g e vovs 1150 min volta g evuds -450 crossin g volta g e (abs) vcross(abs) 250 550 mv crossing voltage (var) d-vcross variation of crossing over all ed g es 140 mv rise time t r v ol = 0.175v, v oh = 0.525v 175 240 700 ps fall time t f v oh = 0.525v v ol = 0.175v 175 242 700 ps rise time variation d-t r 125 ps fall time variation d-t f 125 ps duty cycle d t3 measurement from differential wavefrom 45 51 55 % skew t sk3 v t = 50% 50 100 ps jitter, cycle to cycle t jcyc-cyc 1 v t = 50% 76 150 ps 1 guaranteed b y desi g n, not 100% tested in production. 2 i owt can be varied and is selectable thru the multsel pin. statistical measurement on sin g le ended si g nal usin g mv measurement on single ended si g nal usin g absolute value. mv electrical characteristics - agp t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 66.66 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 33 55 w output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.55 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -33 -33 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.38 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.45 2 ns duty cycle d t1 1 v t = 1.5 v 45 54.4 55 % skew t sk1 1 v t = 1.5 v 243 250 ps jitter t jcyc-cyc 1 v t = 1.5 v 3v66 139 250 ps 1 guaranteed by design, not 100% tested in production.
18 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 electrical characteristics - vch, 48mhz dot, 48mhz, usb t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 48 mhz output impedance r dsp1 1 v o = v dd *(0.5) 20 48 60 w output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -29 -23 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma 48dot rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 0.6 1 ns 48dot fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 0.8 1 ns vch 48 usb rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1 1.2 2 ns vch 48 usb fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1 1.3 2 ns 48 dot duty cycle d t1 1 v t = 1.5 v 45 52.8 55 % vch 48 usb duty cycle d t1 1 v t = 1.5 v 45 53.5 55 % 48 dot jitter t j c y c-c y c 1 v t = 1.5 v 183 350 ps usb to dot skew t sk1 1 v t = 1.5 v (0 or 180 degrees) 0.43 1 ns vch jitter t jcyc-cyc 1 v t = 1.5 v 223 350 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - sdram t a = 0 - 70c; v dd =v ddl 3.3 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp2a 1 v o = v dd *(0.5) 10 20 ? output impedance r dsn2a 1 v o = v dd *(0.5) 10 20 ? output high voltage v oh2a i oh = -28 ma 2.4 v output low voltage v ol2a i ol = 19 ma 0.4 v output high current i oh2a v oh = 2.0 v -42 ma output low current i ol2a v ol = 0.8 v 33 ma rise time t r2a 1 v ol = 0.4 v, v oh = 2.4 v 0.5 2.0 ns fall time t f2a 1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns duty cycle d t2a 1 v t = 1.5 v 45 55 % jitter 1 t cyc-cyc v t = 1.5 v 250.0 ps 1 guaranteed by design, not 100% tested in production.
19 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 electrical characteristics - ref t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 mhz output impedance r dsp1 1 v o = v dd *(0.5) 20 48 60 w output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -29 -23 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1 1.25 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1 1.15 2 ns duty cycle d t1 1 v t = 1.5 v 45 53 55 % jitter t jcyc-cyc 1 v t = 1.5 v 1000 ps 1 guaranteed by design, not 100% tested in production.
20 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
21 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 the impact of asserting the pci_stop# signal will be the following. all pci and stoppable pci_f clocks will latch low in their next high to low transition. the pci_stop# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge. pci_stop# pci_f 33mhz pci 33mhz tsu assertion of pci_stop# waveforms pci_stop# - assertion (transition from logic "1" to logic "0") cpu_stop# cput cpuc the impact of asserting the cpu_stop# pin is all cpu outputs that are set in the i 2 c configuration to be stoppable via assertion of cpu_stop# are to be stopped after their next transition following the two cpu clock edge sampling as shown. the final state of the stopped cpu signals is cput=high and cpuc=low. there is to be no change to the output drive current values. the cput will be driven high with a current value equal to (multsel0) x (i ref), the cpuc signal will not be driven. cpu_stop# - assertion (transition from logic "1" to logic "0") assertion of cpu_stop# waveforms
22 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n a0 808 aaa -- 0.10 -- .004 variations min max min max 48 12.40 12.60 .488 .496 10-0039 n d mm. d (inch) reference doc.: jedec publication 95, mo-153 0.50 basic 0.020 basic see variations see variations see variations see variations 8.10 basic 0.319 basic 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (20 mil) symbol in millimeters in inches common dimensions common dimensions index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c ordering information ics951402 y glf-t example: designation for tape and reel packaging annealed lead free (optional) package type g = tssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y g lf- t
23 integrated circuit systems, inc. ics951402 advance information 0660?05/05/05 index area index area 1 2 n d h x 45 e1 e seating plane seating plane a1 a e - c - b .10 (.004) c .10 (.004) c c l minmaxminmax a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n a 0808 variations minmaxminmax 48 15.75 16.00 .620 .630 10-0034 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions reference doc.: jedec publication 95, mo-118 300 mil ssop n see variations see variations d mm. d (inch) symbol see variations see variations ordering information ics951402 y flf-t example: designation for tape and reel packaging annealed lead free (optional) package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y f lf- t
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